Electronic design automation (EDA) software systems commonly perform routing of networks of circuit designs, such as clock networks (hereafter, clock nets). Usually, net routing can be performed in two phases, where the first phase involves routing guides that attempt to generate timing-aware/timing-based global routing of nets, and the second phase involves detailed routing of nets with specific wires metal traces) based on the routing guides, while attempting to resolve/avoid one or more design rule violations.